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New SPARC solutions are on their way Comments Off on New SPARC solutions are on their way

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The Hotchips conference is over, and with it comes some news from Sun about their SPARC plans. Sun shared details of it’s “Rainbow Falls” processor – the next iteration in the Niagara line.

Boasting 16 cores, each with it’s own cache, it’s an impressive bit of silicon. Each core has 4 Coherency Units (COU). Familiar to anyone who’s played with big Silicon Graphics kit and other cc:NUMA boxes, Coherency Units keep track of memory contents (from L2 cache up to physical RAM).

4 COUs per core, along with 16 seperate L2 caches, is a lot on a single die. To simplify things (and to help improve performance) Sun has added a Core to Cache Crossbar (CCX). Two cores will share a single entry point into the CCX, which is linked to every core on the chip.

It’s essentially a standard switching crossbar – like UPA, Xbow, NUMAlink etc. – except it’s linking cores and L2 caches, not CPUs, RAM, and I/O bays.

All pretty impressive stuff – remember, this is all on the processor die – and it sounds like it would be ideal in a large system. Those M9000 boxes look pretty inviting, especially after the disappointment of the Niagara system board upgrades for the F15k.

And in fact, maybe that’s what Oracle has up it’s sleeve. The Prophets of Larry have said they will be making a major SPARC announcement on October 14th, during Larry’s yearly sermon to the faithful at Oracleworld. (Sorry, guys – I love you really)

With IBM pushing forward development of it’s fearsome Power7 chip, and with Power6 a bit of a monster anyway, Sun clearly needs to keep in the game – especially after (foolishly) canning Rock.

The Oracle announcement will be aimed clearly at blowing the doors off IBM – check their rhetoric and the fuzzy teaser advert on the Sun plus Oracle is Faster page.

Now, there are a number of ways they could bury IBM in the TPC-C benchmarks. Most obvious would be a massive RAC install, probably with Fujitsu’s new 8 way SPARC64 chip. But that wouldn’t really be blowing the Sun SPARC trumpet, would it?

The current top end Niagara box – the T5440 – can have up to four 8 core Niagara CPUs (along with half a terabyte of RAM). It’s pretty good, but again – the only way you can scale is by clustering them. Oracle have an insanely great scalable database solution with Oracle RAC, so it would seem a no-brainer.

However, if Sun are close to releasing Rainbow Falls, they could use the system boards and interconnects from the M9000 chassis to produce a hugely thread-dense NUMA machine. All that coherency hardware makes no sense for a cluster – it’s role is in a big Single System Image (SSI) machine.

We’ll find out in a month.

Sun’s OpenSPARC CPU 2 comments

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Back in 2005 when Sun released the Niagara chip – the UltraSPARC T1 – they also took the unusual step of open sourcing the hardware design of the CPU. Having a ground breaking 8 core, 32 thread CPU was impressive enough, but sharing the internals with anyone who was interested – awesome!

Recently Sun have announced a partnership with Europractice, who are a pan-European group setup to promote student learning of chip design across Europe. It follows on from the successful Eurochip organisation which had similar aims.

With Europractice, Sun are making CPU design details, chip architecture documentation, and FPGA tools available to Universities across Europe. As part of that, Sun are hosting two one day events in London at the beginning of December to spill the beans on all aspects of the OpenSPARC design, as well as some history of the SPARC family.

Sadly this is only open to Europractice members from academic institutions, but Sun have continued their theme of openness by making all the slides and documentation available via their web site.

You’ll need a (free) Sun site login, but head on over to https://wikis.sun.com/display/OpenSPARC/Slidecast+-+All+About+OpenSPARC and download over 5 hours of slides, complete with voice overs and designer notes.

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